I just added you to my track list. Its good to have a working brain around here to learn from.

Despite the 'IBM XL C/C++' is a quite powerful compiler it doesn't solve
any issue which you may have with the Cell/B.E. processor, neither
does C/C++ nor does anything what is supposed to map quite well
to the Cell/B.E. architecture, because these things are not the problem
at all. The problem is what is supposed to sit between your ears.

Nature works in parallel; You, too! Parallel programming concepts are
key, and these concepts mimic most of the things you do day by day
by organizing various things efficiently. Technically, the issue with the
Cell/B.E. processor, due to its parallel nature, is in understanding of
how to shuffle the data around. These requires a "new" understanding
of programming, known as data-driven programming (usually not
common in PC environments) which translates to explicit (user-driven)
memory programming via DMA calls. Open-up the memory controller
for explicit memory programming is key. Doing explicit DMA'ing might
sound difficult at first, but it resembles to what you do in your daily life.
For example, if you go shopping then you build up a shopping list and
buy all the things in one go, instead of buying each item individually.
That's it! The details are, of course, a bit more complicated, but it
essentially breaks down to this. Later on you can layer those explicit
DMA calls away within a library. But you can't start from the opposite
(serious programming assumed), initially, since a uniform memory
architecture on a multi-core system is usually an afterthought (which
btw. does also complicate the hardware in various counter productive
ways) in favor for an ease of programming. And due to the nature of
many different communication patterns of parallel applications
(algorithms) a uniform memory architecture doesn't leant itself quite
well to an efficient utilization of all the processing elements within a
multi-core system. And hence, the layered library (mentioned above),
which btw. will simulate a uniform memory architecture, isn't applicable
to any given parallel workload presented. Therefor, you would build a
certain type of library which fits a certain type/category of parallel
workload(s). But forcing the uniformity right into the hardware would
restrict many parallel workloads from executing efficiently on a
multi-core system. Yes, all in all, this complicates the programming
somewhat. Nevertheless, you have to do it whether you are on Cell/B.E.
or on any another multi-core architecture in gaining efficiency. The
HPC (High-Performance) community faces such issues since the early
days of supercomputing. And no, there won't be a black-box solving
all the issues, due to the massive diversity of parallel programming,
which, by itself, is a research problem at least.

So, how to start?
Kick all the compilers and similar things which offers you not to think
about the real issue, initially. Take a good book on parallel programming,
for example; 'Patterns for Parallel Programming' by Timothy G. Mattson
et al., and crank in all the stuff on all the fancy new processors like,
for example, the Cell/B.E. processor.

I've collected a lot of references on the Cell/B.E. architecture/processor
to server my purpose. You might find it quite useful, too;
http://r.breitrueck.googlep...

The iRT is nice. It runs rather flawlessly on my PS3LinuxBox. IBM has
done a good job in showing off that the Cell/B.E. processor scales quite
well for such workloads.

Another big hit from IBM is the new IBM PowerXCell™ 8i processor to the
serve the HPC community with a full-fledged double-precision extention
of the Cell/B.E. processor;
http://www-03.ibm.com/syste...

Believe!

but teh Cell` haz to suck!.... spew's da Xbot~

@problemsolver (in the game zone since I am out of bubbles for that side)

Great summary and I do like the Patterns for Parallel Programming book. It is a worthy read and I recommend it to anyone who want's to learn Parallel Programming.

not3 not4 not5 not6 not7 but 8 processor in the ps3 play3ond also haze is a good game in my opinion

With respect to my previous post;

I strongly recommend everyone (who is interested, of course) to read the
following paper;

S. Williams, J. Carter, L. Oliker, J. Shalf, K. Yelick,
"Lattice Boltzmann Simulation Optimization on Leading Multicore Platforms",
International Parallel & Distributed Processing Symposium (IPDPS), 2008.
[PDF]: http://www.cs.berkeley.edu/...

This paper clearly shows how the Cell/B.E. processor OWNS the competition
(Intel Clovertown, AMD Operon X2, Intel Itanium2, SUN Niagara2) on a
LBMHD (Lattice Boltzmann Magneto-Hydrodynamics) workload to simulate,
for example, turbulence instabilities in a magnetic fusion device; due to
the way Cell's non-uniform memory architecture can be utilized to gain
efficiency not only measured in GFlop/s, but also in overall power consumption
efficiency!

Note: The kernel-codes used within the paper where already optimized
to give near best result for each architecture! One can see that, for
example, the Intel Clovertown strongly underperforms due to its memory
subsystem.

And just wait for "their" next paper, until the IBM PowerXCell™ 8i
processor kicks in! 8)